| Enabled | Bit | Short | Description |
|---|---|---|---|
no | 0 | fpu | Onboard x87 FPU |
no | 1 | vme | Virtual 8086 mode extensions (such as VIF, VIP, PIV) |
no | 2 | de | Debugging extensions (CR4 bit 3) |
no | 3 | pse | Page Size Extension |
no | 4 | tsc | Time Stamp Counter |
no | 5 | msr | Model-specific registers |
no | 6 | pae | Physical Address Extension |
no | 7 | mce | Machine Check Exception |
no | 8 | cx8 | CMPXCHG8 (compare-and-swap) instruction |
no | 9 | apic | Onboard Advanced Programmable Interrupt Controller |
| 10 | reserved | ||
no | 11 | sep | SYSENTER and SYSEXIT instructions |
no | 12 | mtrr | Memory Type Range Registers |
no | 13 | pge | Page Global Enable bit in CR4 |
no | 14 | mca | Machine check architecture |
no | 15 | cmov | Conditional move and FCMOV instructions |
no | 16 | pat | Page Attribute Table |
no | 17 | pse-36 | 36-bit page size extension |
no | 18 | psn | Processor Serial Number |
no | 19 | clfsh | CLFLUSH instruction (SSE2) |
| 20 | reserved | ||
no | 21 | ds | Debug store: save trace of executed jumps |
no | 22 | acpi | Onboard thermal control MSRs for ACPI |
no | 23 | mmx | MMX instructions |
no | 24 | fxsr | FXSAVE, FXRESTOR instructions, CR4 bit 9 |
no | 25 | sse | SSE instructions (a.k.a. Katmai New Instructions) |
no | 26 | sse2 | SSE2 instructions |
no | 27 | ss | CPU cache implements self-snoop |
no | 28 | htt | Hyper-threading |
no | 29 | tm | Thermal monitor automatically limits temperature |
no | 30 | ia64 | IA64 processor emulating x86 |
no | 31 | pbe | Pending Break Enable (PBE# pin) wakeup capability |